Historically, design engineers implementing high-speed interfaces have met numerous challenges in maintaining interface signal timing relationships and signal quality. Issues such as skew, jitter, crosstalk, and noise have been addressed through a combination of analog circuitry and board/chip physical design rules. Generally, analog circuitry has been used for signal conditioning, filtering, impedance matching, and noise suppression, while physical design rules have targeted skew and crosstalk minimization.
Various approaches have been tried for functional verification of uncertainty in edge placement, programmability of signal delay, and skew over a wide range of values, variable timing relationships between channels, and an ability to vary timing parameters across and outside of the valid range.
A common approach for compensating differences in transmission paths of clock and data signals is use of delay lines in conjunction with multiplexers. Instructions may be provided to a multiplexer for selecting appropriate amount of delay in a clock or a data signal from a tapped delay line. With the introduction of the appropriate amount of delay, proper timing may be re-established.
Thus, it is with respect to these considerations and others that the present invention has been made.